GS4576C09 Datasheet, PDF (3/62 Pages) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

32M x 18 Ball Assignments—144-Ball BGA—Top View
GS4576C09/18/36L
1
2
3
4
5
6
7
8
9
10
11
12
A
V_REF
V_SS
V_EXT
V_SS
V_SS
V_EXT
TMS
TCK
B
V_DD
DNU⁴
DQ4
V_SS
V_SS
DQ0
DNU⁴
V_DD
C
V_TT
DNU⁴
DQ5
V_DDQ
V_DDQ
DQ1 _DNU⁴
V_TT
D
A22¹ DNU^{4 DQ6}
V_SS
V_SS
QK0
QK0
V_SS
E
A21²
DNU⁴
DQ7
V_DDQ
V_DDQ
DQ2
DNU⁴
A20
F
A5
DNU⁴ DQ8
V_SS
V_SS
DQ3 _DNU⁴ QVLD
G
A8
A6
A7
V_DD
V_DD
A2
A1
A0
H
B2
A9
V_SS
V_SS
V_SS
V_SS
A4
A3
J
NF³
NF³
V_DD
V_DD
V_DD
V_DD
B0
CK
K
DK
DK
V_DD
V_DD
V_DD
V_DD
B1
CK
L
REF
CS
V_SS
V_SS
V_SS
V_SS
A14
A13
M
WE
A16
A17
V_DD
V_DD
A12
A11
A10
N
A18
DNU⁴ DQ14
V_SS
V_SS
DQ9 _DNU⁴ A19
P
A15
DNU^{4 DQ15 V}DDQ
V_DDQ DQ10 _DNU⁴
DM
R
V_SS
QK1
QK1
V_SS
V_SS
DQ11 _DNU⁴
V_SS
T
V_TT
DNU⁴ DQ16 ^VDDQ
V_DDQ DQ12 _DNU⁴
V_TT
U
V_DD
DNU^{4 DQ17}
V_SS
V_SS
DQ13 _DNU⁴
V_DD
V
V_REF
ZQ
V_EXT
V_SS
V_SS
V_EXT
TDO
TDI
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address input signal. It may be connected to GND.
3. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
4. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
Rev: 1.04 11/2013
3/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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