GS4576C09 Datasheet, PDF(16/62 Page) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS4576C09 Datasheet, PDF (16/62 Pages) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

◁

GS4576C09/18/36L

Mode Register Set

Mode Register Set controls the operating modes of the memory, including configuration, burst length, test mode, and I/O options.

During an MRS command, the address inputs A0âA17 are sampled and stored in the Mode Register. Except during initialization to

force internal reset, after a valid MRS command, tMRSC must be met before any command except NOP can be issued to the

LLDRAM II. All banks must be idle and no bursts may be in progress when an MRS command is loaded.

Note: Changing the burst length configuration may scramble previously written data. A burst length change must be assumed to

invalidate all stored data.

Mode Register Set

REF

Addr

BA(2:0)

CODE

Rev: 1.04 11/2013

16/62

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

▷