GS4576C09 Datasheet, PDF (33/62 Pages) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

GS4576C09/18/36L
Write Command in Multiplexed Mode
Address Multiplexed Write data transfers are launched with a Write command, as shown below. A valid address must be provided
during the Write command. The Ax address must be loaded on the same true clock crossing used to load the Write command and
the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) is always one cycle longer than the programmed Read Latency (RL).
A Write burst may be followed by a Read command (assuming tRC is met). At least one NOP command is required between Write
and Read commands to avoid data bus contention. The Write-to-Read timing diagrams illustrate the timing requirements for a
Write followed by a Read. Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and tDH. Input data
may be masked high on an associated DM pin. The setup and hold times for the DM signal are tDS and tDH.
Write Command in Multiplexed Mode
WRITE
CK
CK
CS
WE
REF
A(20:0)
Ax
Ay
BA(2:0)
BA
CK
CK
CMD
ADDR
BA
T0
WR
Ax
BA0
DK
DK
DM
D
Write Burst Length 4, Configuration 1 in Multiplexed Mode
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
NOP
WR
NOP
WR
NOP
WR
NOP
WR
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
BA1
BA0
BA3
BA0
WL = 6
D0a
D0b
D0c
D0d
D1a
D1b
Rev: 1.04 11/2013
33/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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