GS8324Z18B Datasheet, PDF (38/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs

Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
V_IHJ3
V_ILJ3
V_IHJ2
V_ILJ2
I_INHJ
I_INLJ
I_OLJ
V_OHJ
V_OLJ
V_OHJC
V_OLJC
2.0
–0.3
0.6 * V_DD2
–0.3
–300
–1
–1
1.7
—
V_DDQ – 100 mV
—
V_DD3 +0.3
0.8
V_DD2 +0.3
0.3 * V_DD2
1
100
1
—
0.4
—
100 mV
V
1
V
1
V
1
V
1
uA
2
uA
3
uA
4
V 5, 6
V 5, 7
V 5, 8
V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V_DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DDQ supply.
6. I_OHJ = –4 mA
7. I_OLJ = + 4 mA
8. I_OHJC = –100 uA
9. I_OHJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Conditions
2.3 V
0.2 V
1 V/ns
1.25 V
1.25 V
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port AC Test Load
DQ
50Ω
30pF^*
V_T = 1.25 V
* Distributed Test Jig Capacitance
Rev: 1.00 10/2001
38/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.