GS8324Z18B Datasheet, PDF (24/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs

Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Power Supply Voltage Ranges
Parameter
Symbol Min.
Typ.
Max.
Unit Notes
3.3 V Supply Voltage
V_DD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
V_DD2
2.3
2.5
2.7
V
3.3 V V_DDQ I/O Supply Voltage
V_DDQ3
3.0
3.3
3.6
V
2.5 V V_DDQ I/O Supply Voltage
V_DDQ2
2.4
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V_DDQ3 Range Logic Levels
Parameter
Symbol Min.
Typ.
Max.
Unit Notes
V_DD Input High Voltage
V_DD Input Low Voltage
V_DDQ I/O Input High Voltage
V_IH
1.7
—
V_DD + 0.3
V
1
V_IL
–0.3
—
0.8
V
1
V_IHQ
1.7
—
V_DDQ + 0.3
V
1,3
V_DDQ I/O Input Low Voltage
V_ILQ
–0.3
—
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V_IHQ (max) is voltage on V_DDQ pins plus 0.3 V.
V_DDQ2 Range Logic Levels
Parameter
Symbol Min.
Typ.
Max.
Unit Notes
V_DD Input High Voltage
V_IH
0.6*V_DD
—
V_DD + 0.3
V
1
V_DD Input Low Voltage
V_IL
–0.3
—
0.3*V_DD
V
1
V_DDQ I/O Input High Voltage
V_IHQ
0.6*V_DD
—
V_DDQ + 0.3
V
1,3
V_DDQ I/O Input Low Voltage
V_ILQ
–0.3
—
0.3*V_DD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V_IHQ (max) is voltage on V_DDQ pins plus 0.3 V.
Rev: 1.00 10/2001
24/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.