GS8324Z18B Datasheet, PDF (26/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs

Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
AC Test Conditions
Parameter
Conditions
Input high level
2.3 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
Output load
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Output Load 2 for t_LZ, t_HZ, t_OLZ and t_OHZ
4. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
Output Load 2
2.5 V
50Ω
30pF^*
DQ
225Ω
VT = 1.25 V
* Distributed Test Jig Capacitance
5pF^{* 225Ω}
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
ZZ and PE Input Current
FT, SCD, ZQ, DP Input Current
Output Leakage Current (x36/x72)
Output Leakage Current (x18)
Output High Voltage
Output High Voltage
Output Low Voltage
Symbol
I_IL
I_IN1
I_IN2
I_OL
I_OL
V_OH2
V_OH3
V_OL
Test Conditions
V_IN = 0 to V_DD
V_DD ≥ V_IN ≥ V_IH
0 V ≤ V_IN ≤ V_IH
V_DD ≥ V_IN ≥ V_IL
0 V ≤ V_IN ≤ V_IL
Output Disable, V_OUT = 0 to V_DD
Output Disable, V_OUT = 0 to V_DD
I_OH = –8 mA, V_DDQ = 2.375 V
I_OH = –8 mA, V_DDQ = 3.135 V
I_OL = 8 mA
Min
–2 uA
–1 uA
–1 uA
–100 uA
–1 uA
–1 uA
–2 uA
1.7 V
2.4 V
—
Max
2 uA
1 uA
100 uA
1 uA
1 uA
1 uA
2 uA
—
—
0.4 V
Rev: 1.00 10/2001
26/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.