GS8324Z18B Datasheet, PDF (15/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs

Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Synchronous Truth Table (x72 and x36 209-Bump BGA)
Operation
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
Deselect Cycle, Power Down
Deselect Cycle, Power Down
D
None H X X L L X X X L L-H High-Z
D
None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down
Deselect Cycle, Continue
D
None X L X L L X X X L L-H High-Z
D
None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst
Read Cycle, Continue Burst
R External L H L L L H X L L L-H Q
B
Next
X X X L H X X L L L-H Q
1,10
NOP/Read, Begin Burst
R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst
B
Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst
W External L H L L L L L X L L-H D
3
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
B
Next X X X L H X L X L L-H D 1,3,10
W
None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst
Clock Edge Ignore, Stall
B
Next X X X L H X H X L L-H High-Z 1,2,3,10
Current X X X L X X X X H L-H -
4
Sleep Mode
None X X X H X X X X X X High-Z
Notes:
1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a
Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin
is sampled low but no Byte Write pins are active, so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.00 10/2001
15/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.