GS8324Z18B Datasheet, PDF (18/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs

Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Pipeline Mode Data I/O State Diagram
Intermediate
BW
R
High Z
(Data In)
D
Intermediate
Intermediate
W
Intermediate
RB
Data Out
(Q Valid)
D
Intermediate
WR
High Z
B
D
Intermediate
Key
Input Command Code
ƒ _Transition
Transition
Current State (n) Intermediate State (N+1) Next State (n+2)
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n
Clock (CK)
n+1
n+2
n+3
Command
ƒ
ƒ
ƒ
ƒ
Current State
Intermediate
State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.00 10/2001
18/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.