GS8324Z18B Datasheet, PDF (22/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs

Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
x18/x36 Mode (PE = 1) Write Parity Error Output Timing Diagram
CK
DQ
D In A
D In B
D In C
D In D
D In E
tKQ
tKQX
tLZ
tHZ
QE
Err A
Err C
DQ
D In A
D In B
D In C
D In D
D In E
tKQ
tKQX
tLZ
tHZ
QE
Err A
Err C
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I_SB2. The duration of
Rev: 1.00 10/2001
22/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.