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GS8324Z18B Datasheet, PDF (30/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs | |||
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Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Pipeline Mode No-Op, Stall and Deselect Timing
CK
CKE
E*
ADV
1
2
3
4
5
6
7
8
9
10
tS tH
tS tH
tS tH
tS tH
W
Bn
A0âAn
A1
A2
DQ
A3
A4
D(A1) Q(A2)
Q(A3)
A5
tKHQZ
D(A4)
Q(A5)
tKQHZ
COMMAND
Write
D(A1)
Read STALL Read
Q(A2)
Q(A3)
Write
D(A4)
STALL NOP
Read DESELECT CONTINUE
Q(A5)
DESELECT
DONâT CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.00 10/2001
30/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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