GS8170LW36 Datasheet, PDF (23/27 Pages) GSI Technology – 18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM

GS8170LW36/72C-333/300/250/200
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
V_IHJ3
2.0
V_DD3 +0.3
V
1
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
V_ILJ3
V_IHJ2
V_ILJ2
I_INHJ
–0.3
0.6 * V_DD2
–0.3
–300
0.8
V_DD2 +0.3
0.3 * V_DD2
1
V
1
V
1
V
1
uA
2
TMS, TCK and TDI Input Leakage Current
I_INLJ
–1
100
uA
3
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
I_OLJ
–1
V_OHJ
1.7
V_OLJ
—
1
uA
4
—
V 5, 6
0.4
V 5, 7
Test Port Output CMOS High
V_OHJC V_DDQ – 100 mV
—
V 5, 8
Test Port Output CMOS Low
V_OLJC
—
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V_DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DDQ supply.
6. I_OHJ = –4 mA
7. I_OLJ = + 4 mA
8. I_OHJC = –100 uA
9. I_OHJC = +100 uA
Rev: 2.03 1/2005
23/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.