GS8170LW36 Datasheet, PDF (17/27 Pages) GSI Technology – 18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM

GS8170LW36/72C-333/300/250/200
Timing Parameter Key—Pipelined Read Cycle Timing
CK
A
E2
DQ(Data Out)
CQ
KHKL
KLKH
KHKH
AVKH
A
KHAX
B
KHCH
KLCL
KHQV
KHQX1
Q(A)
CHQV
KHQZ
KHQX
Q(B)
CHQX
KHCX1
KHCZ
Timing Parameter Key—Late Write Mode Control and Data In Timing
CK
A
E2
DQ(Data Out)
KHKL
KLKH
KHKH
AVKH
A
nVKH
KHAX
B
C
KHnX
DVKH
D(A)
KHDX
D(B)
D(C)
Note: nVKH = EVKH, WVKH, BVKH, etc.
KHnX = KHEX, KHWX, KHBX, etc.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard
(commonly referred to as JTAG). The JTAG Port input interface levels scale with V_DD. The JTAG output drivers are powered by V_DDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI,
and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may
be left floating or tied to either V_DD or V_SS. TDO should be left unconnected.
Rev: 2.03 1/2005
17/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.