GS8170LW36 Datasheet, PDF (20/27 Pages) GSI Technology – 18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM

GS8170LW36/72C-333/300/250/200
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed
ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the
RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the
controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially
loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
Run Test Idle ¹
0
Select DR ¹
0
1 _{Capture DR}
0
Select IR ¹
0
1 _{Capture IR}
0
Shift DR
1
0
1
Exit1 DR
0
Shift IR
1
0
1
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR ₀
1
Exit2 IR
0
1
Update DR
1
0
Update IR
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Rev: 2.03 1/2005
20/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.