GS8170LW36 Datasheet, PDF (11/27 Pages) GSI Technology – 18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM

GS8170LW36/72C-333/300/250/200
CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between
SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point
applications.
Late Write, Pipelined Read Truth Table
CK
E1
(t_n)
E
(t_n)
ADV
(t_n)
W
(t_n)
B
(t_n)
Previous
Operation
Current Operation
DQ/CQ
(t_n)
DQ/CQ
(t_n+1)
0→1 X F
0
XX
X
Bank Deselect
***/***
Hi-Z/Hi-Z
0→1 X X
1
X
X
Bank Deselect
Bank Deselect (Continue)
Hi-Z/Hi-Z
Hi-Z/Hi-Z
0→1 1 T
0
XX
X
Deselect
***/***
Hi-Z/CQ
0→1 X X
1
XX
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
0→1 0 T
0
0T
X
Write
Loads new address
Stores DQx if Bx = 0
***/***
D1/CQ
0→1 0 T
0
0F
X
Write (Abort)
Loads new address
No data stored
***/***
Hi-Z/CQ
0→1 X X
1
XT
Write
Write Continue
Increments address by 1
Stores DQx if Bx = 0
Dn-1/CQ
Dn/CQ
0→1 X X
1
XF
Write
Write Continue (Abort)
Increments address by 1
No data stored
Dn-1/CQ
Hi-Z/CQ
0→1 0 T
0
1X
X
Read
Loads new address
***/***
Q1/CQ
0→1 X X
1
XX
Read
Read Continue
Increments address by 1
Qn-1/CQ
Qn/CQ
Notes:
1. If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.
2. If one or more Bx = 0, then B = “T” else B = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
4. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
5. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
6. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
7. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct
pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the ini-
tial external (base) address.
Rev: 2.03 1/2005
11/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.