MB86391 Datasheet, PDF (7/69 Pages) Fujitsu Component Limited. – MPEG2 1chip Audio/Video Encoder

FUJITSU LIMITED
Proprietary and Confidential
1.3 Specification Overview
1.3.1 Major Items
Table 1.3.1 : Major items
Model
Function
Operating
frequency
Technology
Supply voltage
Power
consumption
Operating
temperature
Package
MB86391
MPEG2 1chip Audio/Video encoder
54MHz (27MHz for some)
[27MHz input clock frequency, 54MHz clock generated by internal PLL]
0.18µm, Al 4 layers
I/O 3.0 to 3.6V, Internal 1.65 to 1.95V
T.B.D
Ta = -20 to 85°C
208pin HQFP(FPT−208P−M04)
1.3.2 Function List
Table 1.3.2 : Function list
Encoding
Video encoder ^{Screen size}
Audio encoder
Video input
interface
Bit rate
Encoding method
Sampling
frequency
Channel count
Audio input
interface
Bit rate
Encoding method
Multiplexer
Stream output
Bit rate
Overall controller
External
SDRAM I/F for
memory
video encoding
interface
Host/SDRAM I/F
Serial interface
Time base corrector
Compliant to ISO/IEC13818−2 (MPEG2 video)MP@ML and
ISO/IEC11172−2 (MPEG1 video)
When interlacing at 29.97Hz
Compatible with size 32m×32n less than 720×480 (m, n : any integers)
When interlacing at 25Hz :
Compatible with size 32m×32n less than 720×576 (m, n : any integers)
D1 8bit parallel, YC multiplex 8bit parallel
Max. 15Mbps
ISO/IEC11172−3 (MPEG1 audio) layer 1/2−compliant
32kHz, 44.1kHz, 48kHz
2 (mono, stereo, dual, joint stereo)
LR multiplex serial
Max. 448kbps
ISO/IEC11172−1 (MPEG1 system)
ISO/IEC13818−1 (MPEG2 system PS/TS)
[Can also output to mono media in ES and PES formats.]
8bit parallel
Max. 20Mbps (CBR/VBR)
Internal 32bit RISC processor
Connects two 16Mbit (1M×16bits) or one 64Mbit (2M×32bits)
Connects two 16Mbit (1M×16bits) or one 64Mbit (2M×32bits)
One internal port for overall controller BOOT and command I/F
Absorbs timing errors due to disarrayed input video images by
temporarily buffering before reading video input data on an SDRAM
connected to the host/SDRAM I/F.
MB86391
Product Specification
Rev. 1.1
12, November 2001
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