MB86391 Datasheet, PDF (22/69 Pages) Fujitsu Component Limited. – MPEG2 1chip Audio/Video Encoder

FUJITSU LIMITED
Proprietary and Confidential
3.1.1 Access by External Master
Shown below are diagrams of timing according to which the external master accesses MB86391
internal resources and SDRAM and peripheral chips (MPEG2 decoder LSI, for example)
connected to this interface.
3.1.1.1 MB86391 Internal Resource Accessing
(a) Write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
XCS5,4,0(O)
XREADY( I/O)
D31:0( I/O)
XBUSEN(O)
BUSDIR(O)
All ‘H ’
All ‘H ’
All ‘ H’
All ‘ H’
Fig. 3.1.1.1a:MB86391 internal resource access timing (Write)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26, 17:2 and D31:0 to
Hi−Z and BUSDIR to 'L' (write direction) and asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0 and asserts the
XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2to
Hi−Z.
(5) After writing data, the MB86391 asserts XREADY and notifies the external master of write
completion.
(6) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state.
Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is
allowed.
MB86391
Product Specification
Rev. 1.1
12, November 2001
18