MB86391 Datasheet, PDF (21/69 Pages) Fujitsu Component Limited. – MPEG2 1chip Audio/Video Encoder

3 Functional Description
FUJITSU LIMITED
Proprietary and Confidential
3.1 Host/SDRAM Interface
The host/SDRAM interface arbitrates bus privilege between the external master connected to this interface and
MB86391 internal resources and also controls access to external resources (such as SDRAM, boot ROM, and
MPEG decoder). Fig. 3.1 shows an example host/SDRAM interface connection. The next and subsequent
chapters show timing diagrams for various accesses.
External
master
MPEG
decoder
XCS4 or 5
XCS0
BA
DIR
OE
Bus transceiver (equivalent to LVx245)
BA
DIR
OE
BCLK(O)[27MHz]
XAS(I/O)
XRDWR(I/O)
XREADY(I/O)
XCS5,4,0(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
ADRS27:26,17:2(I/O)
D31:0( I/O)
BUSDIR(O)
XBUSEN(O)
CS
OE
Boot
ROM
D
A15:0
A18:16
SDRAM
16Mbit×2
(×16bit type)
or
64Mbit×1
(×32bit type)
SPSDCLK(O)[54MHz]
XSPRAS(O)
XSPCAS(O)
XSPWE(O)
XCS, DQM
Fixed to "L"
STDATA2:0(O)
MB86391
Fig. 3.1: Host/SDRAM interface connection (Example)
Note: In the case of a 16Mbit SDRAM, connect ADRS13:2 to BA, A10:0. In the case of a 64Mbit
SDRAM, connect ADRS13:2 to BA1, A10:0. Keep BA0 fixed to ’H’ or ’L.’
Install the MB86391 and the SDRAM as physically close as possible.
Pull up the SPSDCLK signal line with a resistance of 200Ω in the vicinity of the SDRAM.
The SPSDCLK signal line must be in a pattern of a single stroke, from the MB86391, the
sending end, through the SDRAM CLK to the point of connection to the pull−up resistance.
Other signal lines do not require any particular handling such as pull−up. However, take
care to avoid unnecessary routing when designing patterns.
MB86391 can connect each bit width of boot ROM such as ×8bit, ×16bit and ×32bit.
(Recommended ×16bit) Recommended boot ROM size is over 4Mbit.
Fig. 3.1: Host/SDRAM interface connection (Example)
MB86391
Product Specification
Rev. 1.1
12, November 2001
17