MB86391 Datasheet, PDF (30/69 Pages) Fujitsu Component Limited. – MPEG2 1chip Audio/Video Encoder

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3.1.2 Internal Controller Master Accessing
Shown below are diagrams of timing according to which the MB86391 internal controller
accesses peripheral chips (such as the MPEG2 decoder LSI) connected to this interface.
3.1.2.1 External Resource Accessing
(a) Write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XRDWR( I/O)
XAS( I/O)
ADRS27:26, 17:2(I/O)
XCS5,4(O)
XREADY( I/O)
D31:0( I/O)
XBUSEN(O)
BUSDIR(O)
All ‘ H’
All ‘H ’
WA
WD
WA
WD
All ‘ H’
All ‘ H’
Fig. 3.1.2.1a: External resource access timing (Write)
(1) The MB86391 sets XREADY to Hi−Z and asserts XBUSEN to prepare for accessing.
(2) With XCSn (n = 5,4) asserted, the controller selects an external resource and, in conjunction with
XAS assertion, outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0.
(3) When the external resource asserts the XREADY signal, the MB86391 negates XCSn (n = 5,4)
and sets XRDWR to ’H’ (read, normal state) at the same time as the selection is cancelled
(4) The controller negates the XBUSEN and XREADY signals to reset to its normal state.
Note: The external resource needs to be set to Hi−Z after setting XREADY to 'H.'
MB86391
Product Specification
Rev. 1.1
12, November 2001
26