MB86391 Datasheet, PDF (28/69 Pages) Fujitsu Component Limited. – MPEG2 1chip Audio/Video Encoder

FUJITSU LIMITED
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3.1.1.3 External Resource Accessing
(a) Write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
XCS5,4(O)
XREADY( I/O)
D31:0( I/O)
XBUSEN(O)
BUSDIR(O)
All ‘H ’
All ‘H ’
WA
All‘H’
WA
WA
All ‘ H’
WD
WD
All ‘H ’
Fig. 3.1.1.3a: External resource access timing (Write)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to
Hi−Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2, and D31:0 and asserts the
XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26, 17:2to
Hi−Z.
(5) After setting XREADY to Hi−Z, the MB86391 asserts the appropriate XCSn(n = 5,4) and
re−outputs XAS, XRDWR, and ADRS27:26, 17:2 fetched in (4) to the external resource.
(6) The external resource asserts the XREADY signal and notifies that data write is complete.
(7) The MB86391 negates XBUSEN and XREADY, sets BUSDIR to ‘H’ (read direction) and resets to
its normal state.
Notes: After negating XREADY, the next request for bus privilege (asserting XBREQ)
is allowed.
The external resource needs to be set to Hi−Z after setting XREADY to 'H.'
MB86391
Product Specification
Rev. 1.1
12, November 2001
24