MB86391 Datasheet, PDF (35/69 Pages) Fujitsu Component Limited. – MPEG2 1chip Audio/Video Encoder

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3.2 Serial Interface
The serial interface is provided for serial boot and serial API. Since this interface does not control flow with
hardware, you need to control the flow with firmware such as a driver. The firmware dedicated to the internal
controller uses ASCII mode.
3.2.1 Serial Interface Receive Operations
The serial interface supports the following receive data formats:
MODE FM1 FM2 Data section
bit count (N)
ASCII
0 MSB
7
Data32 1
0
32
Description
ASCII code 0x00 to 0x7F and others
32−bit binary data
Fig. 3.2.1a-b shows serial interface receive timings.
SCLK
SDATAIN
FM 1=0 ^{FM 2=}
Bit5
Bit6
Bit4
Bit3
Bit2
Bit1
Bit0 _Parity
Start Bit
Format
Stop Bit
Fig. 3.2.1a: Serial interface receive timings (ASCII mode)
SCLK
SDATAIN
FM1=1 FM2=0 Bit31
Bit30 Bit29 Bit28
Bit27
Bit0
Parity
Start Bit
Format
Stop Bit
Fig.3.2.1b: Serial interface receiver timing (Dara32 mode)
There are 2 type transport mode (SCLK synchronization mode and start-stop synchronization
mode). When using start −stop synchronization mode, pull the SDATAOUT pin down with about
3.3kΩ. When using SCLK synchronization mode, pull the SDATAOUT pin up with about 3.3kΩ. It
is not possible to change the transport mode during working.
In SCLK synchronization mode, data is taken on raising edge of SCLK.
In start−stop synchronization mode, data is taken according to 9600bps with reference to the
StartBit falling edge of the SDATAIN signal regardless of SCLK.
Use even parity from FM1 through DataN. After the parity bit, 1 is needed as StopBit. However,
if 0 is received at this point, it is recognized as a break signal and invalidates receive data.
MB86391
Product Specification
Rev. 1.1
12, November 2001
31