MB86391 Datasheet, PDF (43/69 Pages) Fujitsu Component Limited. – MPEG2 1chip Audio/Video Encoder

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(1) When ready to receive streams, set STREQ to 'H.'
(2) When valid data exists, the MB86391 changes STEN ’H’→’L’ →’H’ at STDATA. It simultaneously
sets the TSPSSYNC signal to 'H' at the sync byte "0x47" if the stream is TS, and at the pack start
code "0x000001BA" or at the leading byte of the program end code "0x 000001B9" if the stream is
PS.
Note: Limit the duration during which STREQ is set to ’L’ while encoding to a few tens
of clocks. The bit rate must also be maintained on the average (The MB86391 is
equipped with an internal buffer to temporarily store bit streams. However, the
buffer fails if bit streams are not read for a lengthy period of time.)
(c) External clock sync mode(CBR)
This mode is for real time transfer function products. The PCR(SCR) is made by STCLK.
STCLK(I)
STREQ(I)
STEN(O)
STDATA(O)
TSPSSYNC(O)
Valid Valid
Valid Valid
Fig. 3.6c: External clock mode (CBR)
(1) Input the transfer clock to STCLK according to the bit and set STREQ to 'H.'
(2) While transferring, the MB86391 outputs 'H' to STEN at all times and outputs valid data according
to the external clock STCLK. It also simultaneously sets the TSPSSYNC signal to 'H' at the sync
byte "0x47" if the stream is TS, and at the pack start code "0x000001BA" or at the leading byte of
the program end code "0x000001B9" if the stream is PS.
Note: STCLK should be input over 1/8 x system bit-rate. (EX: When the system bit-rate
is 8Mbps, STCLK should be over 1MHz.) When STCLK is more high frequency
than system bit-rate which is setted, stuffing is implemented.
(d) External clock sync mode (VBR)
This mode is for real time transfer function products. The PCR(SCR) is made bySTCLK.
STCLK(I)
STREQ(I)
STEN(O)
STDATA(O)
Valid Valid
TSPSSYNC(O)
Fig. 3.6d: External clock mode (VBR)
Valid Valid
MB86391
Product Specification
Rev. 1.1
12, November 2001
39