MB82DBS08164C-70L Datasheet, PDF (7/58 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS08164C-70L
■ FUNCTIONAL DESCRIPTION
This device supports asynchronous read & normal write operation and synchronous burst read and burst write
operations for faster memory access and features four kinds of power down modes for power saving as user
configurable option.
• Power-up
It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing".
After Power-up, the device defaults to asynchronous read & normal write operation mode with sleep power down
feature.
• Configuration Register
The Configuration Register(CR) is used to configure the type of device function among optional features. Each
selection of features is set through CR Set sequence after power-up. If CR Set sequence is not performed after
power-up, the device is configured for asynchronous operations with sleep power down feature as default con-
figuration. The content of CR can be confirmed using CR Verify sequence.
• CR Set & Verify Sequence
The CR Set and CR Verify requires total 6 read/write operations with unique address. The device should be in
standby mode in the interval between each read/write operation. The following table shows the detail sequence
of CR Set and CR Verify.
Cycle #
1st
2nd
3rd
4th
5th
6th
Address
7FFFFFh (MSB)
7FFFFFh
7FFFFFh
7FFFFFh
7FFFFFh
7FFFFFh
CR Set
Operation
Data
Read
Read Data (RDa)
Write
RDa
Write
RDa
Write
CR Key 0
Write
CR Key 1
Write
CR Key 2
CR Verify
Operation
Data
Read
Read Data (RDa)
Write
RDa
Write
RDa
Write
CR Key 0
Read
CR Key 1
Read
CR Key 2
The first cycle is to read from most significant address(MSB).
The second and third cycles are to write to MSB. If the second or third cycle is written into the different address,
the CR Set is cancelled and the data written by the second or third cycle is valid as a normal write operation. It
is recommended to write back the data(RDa) read by first cycle to MSB in order to secure the data.
The fourth cycle is to write the appropriate “CR Key 0” to select the CR Set or CR Verify.
The fifth and sixth cycle is to access into MSB to set the “CR Keys” or to verify the “CR Keys”. Refer to the "CR
Key Table". If the fourth to sixth cycle are not access into MSB , the CR Set or CR Verify are cancelled and CR
input or output data will be invalid.
Once this CR Set sequence is performed from an initial CR Set to the other new CR Set, the written data stored
in the memory cell array may be lost. Therefore CR Set sequence should be performed prior to regular read/
write operation if necessary to change from the default configuration.
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