MB82DBS08164C-70L Datasheet, PDF (21/58 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS08164C-70L
(3) Synchronous Operation - Clock Input (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit Notes
RL = 7
9.5
⎯
ns *1
Clock Period
RL = 6
RL = 5
12
⎯
ns *1
tCK
13
⎯
ns *1
RL = 4
18
⎯
ns *1
Clock High Time
tCKH
3
⎯
ns
Clock Low Time
tCKL
3
⎯
ns
Clock Transition Time
tCKT
⎯
1.5
ns *2
*1 : Clock period is defined between valid clock edges.
*2 : Clock transition time is defined between VIH (Min) and VIL (Max)
(4) Synchronous Operation - Address Latch (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit Notes
Address Setup Time to CE1 Low
tASCL
−2
⎯
ns *1
Address Setup Time to ADV Low
tASVL
−2
⎯
ns *2
Address Hold Time from ADV High
tAHV
0
⎯
ns
ADV Low Pulse Width
tVPL
7
⎯
ns *3
RL = 6, 7
3
⎯
ADV Low Setup Time to CLK
tVSCK
ns *4
RL = 4, 5
5
⎯
RL = 6, 7
3
⎯
CE1 Low Setup Time to CLK
tCLCK
ns *4
RL = 4, 5
5
⎯
ADV Low Hold Time from CLK
tCKVH
1
⎯
ns *4
*1 : tASCL is applicable if CE1 is brought to Low after ADV is brought to Low.
*2 : tASVL is applicable if ADV is brought to Low after CE1 is brought to Low.
*3 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and
tASVL (or tASCL) must be equal or greater than the specified minimum value of tVPL.
*4 : Applicable to the 1st valid clock edge.
21