MB82DBS08164C-70L Datasheet, PDF (14/58 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS08164C-70L
• Address Latch by ADV
The ADV latches the valid address presence on address inputs. During synchronous burst read/write operation
mode, all the addresses are determined on the rising edge of ADV when CE1 = L. The specified minimum value
of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied.
Valid address must be determined with specified setup time against either the falling edge of ADV or falling edge
of CE1 whichever comes late. And the determined valid address must not be changed during ADV = L period.
• Burst Length
Burst Length is the number of word to be read or written during synchronous burst read/write operation as the
result of a single address latch cycle. It can be set on 8,16 words boundary or continuous for entire address
through CR Set sequence. The burst type is sequential that is incremental decoding scheme within a boundary
address. Starting from an initial address being latched, the device internal address counter assigns +1 to the
previous address until reaching the end of boundary address and then wrap round to least significant address
(= 0). After completing read data output or write data latch for the set burst length, operation automatically ended
except for continuous burst length. When continuous burst length is set, read/write is endless unless it is termi-
nated by the rising edge of CE1.
• Write Control
The device has two types of WE signal control method, "WE Level Control" and "WE Single Clock Pulse Control",
for synchronous burst write operation. It is configured through CR Set sequence.
CLK
Address
0
1
2
3
4
5
6
Valid address
ADV
CE1
WAIT
WE Level Control
WE
High-Z
tCLTH
tWLTH
RL = 5
tWLD
DQ ^[Input]
WE Single Clock Pulse Control
tWSCK
WE
DQ [Input]
tCKWH
D1
D2
D3
D4
D1
D2
D3
D4
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