MB82DBS08164C-70L Datasheet, PDF (10/58 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS08164C-70L
• Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode
and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down
mode.
This device has four power down modes, Sleep, 16 M-bit Partial, 32 M-bit Partial, and 64 M-bit Partial. Those
power down modes are effective when RA = 1. The selection of power down mode is set through CR Set
sequence. Each mode has following data retention features.
Mode
Sleep [default]
16 M-bit Partial
32 M-bit Partial
64 M-bit Partial
Data Retention Size
No
16 M bits
32 M bits
64 M bits
Retention Address
N/A
000000h to 0FFFFFh
000000h to 1FFFFFh
000000h to 3FFFFFh
The default state after power-up is Sleep and it is the lowest power consumption. However all data will be lost
once CE2 is brought to Low for Power Down. It is not required to perform CR Set sequence to set to Sleep mode
after power-up in case of asynchronous operation.
When RA = 0, CE2 brought to Low reset the device to asynchronous standby state regardless PS set value.
• Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that synchronized to the microcontroller
or system bus frequency. Configuration Register(CR) Set is required to perform a burst read & write operation
after power-up. Once CR Set sequence is performed to select the synchronous burst mode, the device is
configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through
CR Set sequence together with the operation mode. In order to perform synchronous burst read & write operation,
it is required to control new signals, CLK, ADV and WAIT that Low Power SRAMs don’t have.
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