MB86330 Datasheet, PDF (34/46 Pages) Fujitsu Component Limited. – 16-bit Fixed-point DSP

MB86330
3. BOOT Timing
Performing BOOT processing requires satisfaction of the following operation.
(1) Take setup of two or more MCLK clocks from a fall rising edge.
(2) Fetch information about the BOOT pin at a fall rising edge, and the BTACT pin will be set at “H”.
(3) Reset the BOOT pin at least two MCLK clocks after a fall edge observed at the BTACT pin.
(4) When the BTACT pin is changed from “H” to “L”, BOOT operation is terminated.
• PM = 0 (When PLL is not used)
XRST
MCLK
[RESET]
SCKOUT
BOOT
BTACT
(1)
(3)
(2)
• PM = 1 (When PLL is used)
XRST
MCLK
[PLL-clk]
[RESET]
SCKOUT
BOOT
BTACT
(1)
(3)
(2)
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