MB86330 Datasheet, PDF (20/46 Pages) Fujitsu Component Limited. – 16-bit Fixed-point DSP

MB86330
s DETAILED DESCRIPTION OF SPECIAL REGISTERS
(1) Status Register
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IT OV3 OV1 INT2 INT1 INT0 MDMA CP RND ITG V3 V2 V1
N
Z
C
Bit abbreviation
Bit name
C
Carry flag
Z
Zero flag
N
Negative flag
V1
Overflow flag 1
V2
Overflow flag 2
V3
Overflow flag 3
ITG
RND
Operating mode
specification flag
Rounding mode setup
CP
MDMA
INT0
INT1
INT2
OV1
Clip flag
DMA enable flag
Interrupt enable flag
Interrupt enable flag
Interrupt enable flag
V1 interrupt enable flag
OV3
V3 interrupt enable flag
IT
20
Interrupt enable flag
Description
Set when carry occurs as a result of operation execution.
Reset when no carry occurs.
Not changed by transfer instruction execution.
Set when the operation result is 0.
Reset when the operation result is not 0.
Not changed by transfer instruction execution.
Set when the operation result is smaller than 0.
Reset when the operation result is equal to or greater than 0.
Not changed by transfer instruction execution.
Set when the operation result overflows.
Reset when the operation result does not overflow.
Not changed by transfer instruction execution.
Set when the operation result overflows.
Set V2 is reset only by hardware or by ST programming by the
transfer instruction.
Not changed by transfer instruction execution.
Set when the operation result of an instruction stored in CX or DX
cannot be expressed by 32 bits (but by 40 bits).
Reset when the operation result can be expressed by 32 bits.
Specify this when executing multiplication in integral mode.
Used to set ON/OFF of rounding processing when data is
transferred from a register consisting of 32 or more bits to a 16-bit
register.
Used to specify whether the operation result is to be clipped
when overflow occurs during the operation.
Enables a DMA interrupt. (0: Disabled)
INT0 (SMODE) interrupt enable flag
0: Disabled, 1: Enabled
INT1 interrupt enable flag
0: Disabled, 1: Enabled
INT2 interrupt enable flag
0: Disabled, 1: Enabled
Operation overflow interrupt enable flag. An interrupt is generated
when V1 is set.
0: An interrupt is disabled. 1: An interrupt is enabled.
Operation overflow interrupt enable flag. An interrupt is generated
when V3 is set.
0: An interrupt is disabled. 1: An interrupt is enabled.
OV1, OV3 and INT0 to INT7 interrupt enable flag
0: An interrupt is disabled. 1: An interrupt is enabled.