MB86330 Datasheet, PDF (19/46 Pages) Fujitsu Component Limited. – 16-bit Fixed-point DSP

MB86330
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• Shift register (SFT)
The SFT register consists of signed 6 bits. This shift value storage register stores the number of bits shifted
during execution of the shift instruction.
• Shift register (SFTV)
The SFTV register, which consists of 16 bits, is used to store the results of CMLT and CMGT instruction.
• Status register (ST)
The status register, which consists of 16 bits, is assigned bits for storing information about results of operations
(carry and overflow) and for setting operating mode.
• Mode register (MODE)
This register is used to specify modes of operations and transfer, and interrupts.
• Flag holding register (DRF)
This register holds flags for the DO, REP and REP2 instructions. It can process only PUSH/POP. This register
is cleared by the PUSH instruction.
• DMA counters (DMAC0 to DMAC3)
When a DMA interrupt occurs, this register stores the address of the data transfer source or the data transfer
destination.
• Program counter (PC)
The program counter, which consists of 16 bits, points to the memory address that stores an instruction code
to be executed by the CPU. While it is updated automatically by instruction execution, the program counter
can be rewritten by a conditional branch, a subroutine call instruction, an interrupt, and a reset. Executing the
repeat instruction stops a program counter update.
• Stack pointer (SP)
The stack pointer, which consists of 16 bits, stores addresses for saving and transferring the contents of
registers upon execution of the PUSH/POP instruction, the subroutine call instruction, or an interrupt.
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