MB86330 Datasheet, PDF (15/46 Pages) Fujitsu Component Limited. – 16-bit Fixed-point DSP

MB86330
s BASIC PIPELINE OPERATION
The DSP splits the contents of processing in one cycle to increase the number of pipeline sectors for high-speed
operation. For operations using product adders such as product addition and multiplication, and for operations
using 40-bit adders such as 40-bit addition, the processing latency is two cycles.
Pipeline phase
Operation (latency 1)
Operation (latency 2)
Transfer (Reg-Reg R/W)
Transfer (Mem Read)
Transfer (Mem Write)
PC
DE1
DE2
EX1
EX2
PC
dec1
adr
dec2
ALU1
PC
dec1
adr
dec2
ALU2
PC
dec1
adr
dec2
R/W
PC
dec1
adr
dec2
R
PC
dec1
adr
dec2
[adr]
W
PC: Program fetch cycle
DE1: Decode 1st. cycle
DE2: Decode 2nd. cycle
EX1: Execute 1st. cycle
EX2: Execute 2nd. cycle
dec1: 1st. decoding
dec2: 2nd. decoding
adr: Address generation
[adr] Address maintenance
ALU: Operation
R: Reading
W: Writing
s PRODUCT ADDITION
For product addition and multiplication, the latency is two cycles. Because it is provided with a dual product
adder (MAC) for alternate processing every cycle, however, the DSP can process n successive product addition
(multiplication) steps in (n + 1) cycles.
Operation latency 2
MSM (1)
MSM (3)
MSM (2)
MSM (4)
MSM (n - 1)
MSM (n)
(n + 1) cycles
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