MB81EDS516545 Datasheet, PDF (34/60 Pages) Fujitsu Component Limited. – MEMORY Consumer FCRAM CMOS 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
2. AC Characteristics
Parameter
(Under recommended operating conditions unless otherwise noted)^{*1, *2}
Value
Symbol
Unit
Min.
Max.
DQ Output Access Time from CK/CK (tCK = tCK min)*^3, *^4, *⁷
tAC
2
6
ns
RDQS Output Access Time from CK/CK *^3, *⁴
tDQSCK
2
6
ns
Clock High Level Width *³
tCH
2
⎯
ns
Clock Low Level Width *³
tCL
2
⎯
ns
Delay between CK and CK *⁴
tDC
0.45
0.55
tCK
CL = 2
15
Clock Cycle Time
CL = 3
7.4
tCK
⎯
ns
Tj ≤ + 105 °C
4.6
CL = 4
Tj ≤ + 125 °C
5
Tj ≤ + 105 °C
0.4
⎯
ns
DQ and DM Input Setup Time*³
tDS
Tj ≤ + 125 °C
0.5
⎯
ns
DQ and DM Input Hold Time*³
Tj ≤ + 105 °C
0.4
⎯
ns
tDH
Tj ≤ + 125 °C
0.5
⎯
ns
DQ and DM Input Pulse Width
tDIPW
0.35
⎯
tCK
Address and Control Input Setup Time *³
tIS
0.9
⎯
ns
Address and Control Input Hold Time *³
tIH
0.9
⎯
ns
Address and Control Input Pulse Width
tIPW
0.6
⎯
tCK
DQ Low-Z Time from CK/CK *^3, *⁵
tLZ
0
⎯
ns
DQ High-Z Time from CK/CK *^3, *^5, *⁶
tHZ
⎯
6
ns
RDQS to DQ Skew *⁴
tDQSQ
⎯
0.4
ns
DQ Output Hold Time from RDQS *^3, *⁴
tQH
tDC − 0.5
⎯
ns
WRIT Command to 1st WDQS Latching Transition
tDQSS
0.75
1.25
tCK
WDQS Input High Level Width
tDQSH
0.35
⎯
tCK
WDQS Input Low Level Width
tDQSL
0.35
⎯
tCK
WDQS Falling Edge to CK Setup Time
tDSS
0.2
⎯
tCK
WDQS Falling Edge Hold Time from CK
tDSH
0.2
⎯
tCK
MRS Command Period
tMRD
2
⎯
tCK
Write Preamble Setup Time
tWPRES
0
⎯
ns
Write Postamble Time
tWPST
1
⎯
tCK
(Continued)
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DS05-11463-1E