MB81EDS516545 Datasheet, PDF (20/60 Pages) Fujitsu Component Limited. – MEMORY Consumer FCRAM CMOS 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
■ BANK OPERATION COMMAND TABLE
Minimum clock latency or delay time for single bank operation
2nd Command (same bank)
MRS
tMRD
tMRD
⎯
⎯
⎯
⎯
tMRD
tMRD
tMRD
tMRD
tMRD
tMRD
tMRD
tMRD
⎯
ACT
⎯
⎯
tRCD
*4
tRCD
tRCD
*5
tRCD
⎯
tRAS
tRAS
⎯
⎯
⎯
tRAS
⎯
⎯
*6
*6
READ ⎯ ⎯
1
1
BL/2 BL/2
1
+CL +CL
*3
1
*3
1
⎯
⎯
⎯
*3
1
⎯
⎯
*1, *2
READA ^BL/2
+ tRP
BL/2
+ tRP
⎯
⎯
⎯
WRIT ⎯
*6
*6
⎯
2
2
1
+ tWTR + tWTR
WRITA
*1, *2
BL/2
+1
BL/2
+1
⎯
⎯
⎯
+ tDAL
+ tDAL
READ -
BST
⎯
⎯
1
1
CL
WRIT -
BST
⎯
⎯
1
+ tWTR
1
+ tWTR
1
⎯
BL/2
+ tRP
BL/2
+ tRP
BL/2
+ tRP
*1
BL/2
+ tRP
*1, *2
BL/2
+ tRP
BL/2
+ tRP
BL/2
+ tRP
BL/2
+ tRP
⎯
*3
*3
*3
BL/2 BL/2
BL/2
1
1
+1
+1
⎯
⎯
⎯
+1
⎯
⎯
+ tWR
+ tWR
+ tWR
BL/2
BL/2
BL/2
*1
BL/2
*1, *2
BL/2
BL/2
BL/2
BL/2
⎯
+1
+1
+1
+1
+1
+1
+1
+1
⎯
+ tDAL
+ tDAL
+ tDAL
+ tDAL
+ tDAL
+ tDAL
+ tDAL
+ tDAL
CL
*3
1
*3
1
⎯
⎯
⎯
1
⎯
⎯
1
1
*3
*3
1
1
⎯
+ tWR
+ tWR
⎯
⎯
1
+ tWR
⎯
⎯
PRE
*1, *2
tRP
tRP
⎯
⎯
⎯
⎯
tRP
1
1
*1
tRP
*1, *2
tRP
tRP
1
tRP
⎯
PALL
*2
tRP
tRP
⎯
⎯
⎯
⎯
tRP
1
1
tRP
*2
tRP
tRP
1
tRP
⎯
REF
tREFC
tREFC
⎯
⎯
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
⎯
SELFX tREFC
tREFC
⎯
⎯
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
⎯
MACT ⎯
⎯
*7
tRCD
*7
tRCD
*7
tRCD
*7
tRCD
⎯
tRAS 1 + tRAS
⎯
⎯
⎯ 1 + tRAS ⎯
⎯
MPRE
*1, *2
tRP
tRP
⎯
⎯
⎯
⎯
tRP
1
1
*1
tRP
*1, *2
tRP
tRP
1
tRP
⎯
BREF
RC x
tREFC
RC x
tREFC
⎯
⎯
⎯
⎯
⎯
RC x
tREFC
RC x
tREFC
RC x
tREFC
RC x
tREFC
RC x
tREFC
RC x
tREFC
RC x
tREFC
*8
tREFC
BREFX tREFC
tREFC
⎯
⎯
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
⎯
“ - ” : illegal
*1: Assume all banks are in IDLE state.
*2: Assume output is in High-Z state.
*3: Assume tRAS (Min.) is satisfied.
*4: ACT to READA interval must be longer than tRAS - BL/2.
*5: ACT to WRITA interval must be longer than tRAS - (1 + BL/2 + tWR).
*6: Assume appropriate DM masking.
*7: 1st read or write access must be allowed for appropriate bank specified in the ACT and MACT commands of
“■COMMAND TRUTH TABLE”.
*8: BREFX command can be issued only when Background Refresh is in progress.
20
DS05-11463-1E