MB81EDS516545 Datasheet, PDF (27/60 Pages) Fujitsu Component Limited. – MEMORY Consumer FCRAM CMOS 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
17. DEEP POWER DOWN ENTRY (DPD)
DEEP POWER DOWN ENTRY (DPD) commands to drive the device in Deep Power Down mode which is the
lowest power consumption but all stored data and the contents of mode registers will be lost. During Deep Power
Down state, all inputs signals except for CKE are a “don't care” and all DQs and RDQS will be in High-Z. Deep
Power Down mode must be entered on conditions that all DQs are in High-Z and all banks are in IDLE state.
18. DEEP POWER DOWN EXIT (DPDX)
DEEP POWER DOWN EXIT (DPDX) commands to resume the device from Deep Power Down mode. Power
up initialization procedure must be performed after DPDX commands. Refer to the “Power Up Initialization” in
“■ FUNCTIONAL DESCRIPTION”.
19. MULTI BANK ACTIVE (MACT)
MULTI BANK ACTIVE (MACT) command activates 2 banks simultaneously selected by BA1. SA must be High to
issue MACT command. BA1 determines the target bank group is either Bank 0 & 1 or Bank 2 & 3. And BA0
determines the bank where 1st read or write access can be performed. If MACT command is issued to Bank 0
(or Bank 2) with RA = N, same Row Address of RA = N is activated for Bank 1 (or Bank 3) and 1st read or write
access must be allowed for RA=N of Bank 0 (or Bank 2). If MACT command is issued to Bank 1 (or Bank 3)
with RA = N, next Row Address of RA = N + 1 is activated for Bank 0 (or Bank 2) and 1st read or write access
must be allowed for RA = N of Bank 1 (or Bank 3). If MACT command is issued to Bank 1 (or Bank 3) with RA =
FFFh, internal row address counter is wrap around therefore activated Row Address is FFFh for Bank 1 (or Bank
3) and 000h for Bank 0 (or Bank 2).
Command Truth Table of ACT and MACT
Command
Symbol
SA
BA1
BA0
Row Address
A[12:0]
LL
BANK
ACTIVE
LH
ACT L
HL
HH
LL
MULTI BANK
ACTIVE
MACT
H
L
H
H
L
HH
RA = N
RA = N
1st access
Bank
RA
Bank 0 RA = N
Bank 1 RA = N
Bank 2 RA = N
Bank 3 RA = N
Bank 0 RA = N
Bank 1 RA = N
Bank 2 RA = N
Bank 3 RA = N
2nd access
Bank
RA
NA
NA
NA
NA
Bank 1 RA = N
Bank 0 RA = N + 1
Bank 3 RA = N
Bank 2 RA = N + 1
The following memory map example enables to issue effective MACT command for 2-bank interleave access
between Bank 0 and Bank 1 or Bank 2 and Bank 3.
Memory Map Example for 2-bank interleave access by MACT command
Bank
0
1
0
1
→
0
1
0
1
0
1
→
0
1
0
1
RA
000h
001h
→
N-1
N
N+1
→
FFFh
FFFh
Bank
2
3
2
3
→
2
3
2
3
2
3
→
2
3
2
3
RA
000h
001h
→
N-1
N
N+1
→
FFFh
FFFh
DS05-11463-1E
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