MC94MX21 Datasheet, PDF (94/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Specifications
1
VSYNC
PIXCLK
6
5
4
DATA[7:0]
Valid Data
2
3
Valid Data
Valid Data
Figure 84. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 45. Non-Gated Clock Mode Parameters¹
Number
Parameter
Minimum
1
csi_vsync to csi_pixclk
2
csi_d setup time
3
csi_d hold time
4
csi_pixclk high time
5
csi_pixclk low time
6
csi_pixclk frequency
9 * T_HCLK
1
1
T_HCLK
T_HCLK
0
1. HCLK = AHB System Clock, T_HCLK = Period of HCLK
Maximum
–
–
–
–
–
HCLK / 2
Unit
ns
ns
ns
ns
ns
MHz
3.22.3 Calculation of Pixel Clock Rise/Fall Time
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time
and setup time based on the following assumptions:
Rising-edge latch data
• max rise time allowed = (positive duty cycle - hold time)
• max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
• max rise time = (period / 2 - hold time)
• max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
≥ max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
≥ max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
• max fall time allowed = (negative duty cycle - hold time)
• max rise time allowed = (positive duty cycle - setup time)
MC94MX21 Technical Data, Rev. 1.4
94
Freescale Semiconductor