MC94MX21 Datasheet, PDF (53/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Specifications
Table 33. SSI to SAP Ports Timing Parameters (Continued)
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
Synchronous Internal Clock Operation (SAP Ports)
31 SRXD setup before (Tx) CK falling
32 SRXD hold after (Tx) CK falling
23.00
–
21.41
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (SAP Ports)
33 SRXD setup before (Tx) CK falling
34 SRXD hold after (Tx) CK falling
1.20
–
0.88
–
ns
0
–
0
–
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 34. SSI to SSI1 Ports Timing Parameters
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation¹ (SSI1 Ports)
1 (Tx/Rx) CK clock period¹
90.91
–
2 (Tx) CK high to FS (bl) high
-0.68
-0.15
3 (Rx) CK high to FS (bl) high
-0.96
-0.27
4 (Tx) CK high to FS (bl) low
-0.68
-0.15
5 (Rx) CK high to FS (bl) low
-0.96
-0.27
6 (Tx) CK high to FS (wl) high
-0.68
-0.15
7 (Rx) CK high to FS (wl) high
-0.96
-0.27
8 (Tx) CK high to FS (wl) low
-0.68
-0.15
9 (Rx) CK high to FS (wl) low
-0.96
-0.27
10 (Tx) CK high to STXD valid from high impedance
-1.68
-0.36
11a (Tx) CK high to STXD high
-1.68
-0.36
11b (Tx) CK high to STXD low
-1.68
-0.36
12 (Tx) CK high to STXD high impedance
-1.58
-0.31
13 SRXD setup time before (Rx) CK low
20.41
–
14 SRXD hold time after (Rx) CK low
0
–
90.91
-0.68
-0.96
-0.68
-0.96
-0.68
-0.96
-0.68
-0.96
-1.68
-1.68
-1.68
-1.58
20.41
0
–
ns
-0.15
ns
-0.27
ns
-0.15
ns
-0.27
ns
-0.15
ns
-0.27
ns
-0.15
ns
-0.27
ns
-0.36
ns
-0.36
ns
-0.36
ns
-0.31
ns
–
ns
–
ns
15 (Tx/Rx) CK clock period¹
16 (Tx/Rx) CK clock high period
17 (Tx/Rx) CK clock low period
18 (Tx) CK high to FS (bl) high
19 (Rx) CK high to FS (bl) high
External Clock Operation (SSI1 Ports)
90.91
36.36
36.36
10.22
10.79
–
–
–
17.63
19.67
90.91
36.36
36.36
8.82
9.39
–
ns
–
ns
–
ns
16.24
ns
18.28
ns
MC94MX21 Technical Data, Rev. 1.4
Freescale Semiconductor
53