MC94MX21 Datasheet, PDF (16/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Specifications
Table 7 shows the power consumption for the device.
Table 7. Power Consumption
ID Parameter
Conditions
Symbol
Typ Max Units
1 Run Current QVDD = QVDDX = 1.80V (333MHz), NVDD1 = 1.7V.
NVDD2 through NVDD6 = VDDA = 3.1V.
Core = 333 MHz, System = 111 MHz.
I_QVDD + I_QVDDX
I_NVDD1
180 – mA
8 – mA
MPEG4 Playback (QVGA) from MMC/SD card, 30fps, _{INVDD2 through INVDD6 + IVDDA 6.6 – mA}
44.1kHz audio.
2 Sleep Current Standby current with Well Biasing System enabled.
Well Bias Control Register (WBCR) must be set as
follows:
WBCR:
CRM_WBS bits = 01
CRM_WBFA bit = 1
CRM_WBM bits = 001
CRM_SPA_SEL bit = 1
FMCR bit = 1
I_STBY
QVDD = QVDDX = 1.80V, 70° –
QVDD = QVDDX = 1.80V, 25° –
6 mA
3 mA
For WBCR definition refer to System Control Chapter
in the reference manual.
3.4 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency (HCLK) from 0 MHz to 117 MHz (core operating frequency 333 or
350 MHz) with an operating supply voltage from V_{DD min} to V_{DD max} under an operating temperature
from T_L to T_H. All timing is measured at 30 pF loading with the exception of fast I/O signals which is
measured at 21 pF at a 6.5 mA drive strength setting. Refer to the reference manual’s System Control
Chapter for details on drive strength settings.
Table 8. 32k/26M Oscillator Signal Timing
Parameter
EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL
EXTAL32k input jitter (peak to peak) for MCUPLL only
EXTAL32k startup time
Minimum
–
–
800
RMS
5
5
–
Table 9. CLKO Rise/Fall Time (at 30pF Loaded)
Best Case Typical Worst Case Units
Rise Time
0.80
1.00
1.40
ns
Fall Time
0.74
1.08
1.67
ns
Maximum Unit
20
ns
100
ns
–
ms
MC94MX21 Technical Data, Rev. 1.4
16
Freescale Semiconductor