MC94MX21 Datasheet, PDF (2/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Introduction
For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash
devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC)
and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN,
Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers.
The device is packaged in a 289-pin MAPBGA.
System Control
JTAG/Multi ICE
System Boot
Clock Management
Standard System I/O
Timers x 3
PWM
WDOG
RTC
GPIO
DMAC
Human Interface
CSI
LCD Controller
SLCD Controller
Keypad
i.MX21
ARM9 Platform
ARM926EJ-S
MAX
I Cache
MMU
D Cache
Bus Control
Internal Control Memory Control
Enhanced Multimedia Accelerator
(eMMA)
Pre- and Post- Processing
Video Accelerator
Connectivity
CSPI x 3
SSI x 2
I²C
Audio Mux
UART x 4
1-WIRE
IrDA
USB OTG/ 2 Hosts
Memory Expansion
MMC/SD x 2
PCMCIA/CF
Memory Interface
SDRAMC
EIM/BMI
NFC
Figure 1. i.MX21 Functional Block Diagram
1.1 Conventions
This document uses the following conventions:
• OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
• Logic level one is a voltage that corresponds to Boolean true (1) state.
• Logic level zero is a voltage that corresponds to Boolean false (0) state.
• To set a bit or bits means to establish logic level one.
• To clear a bit or bits means to establish logic level zero.
• A signal is an electronic construct whose state conveys or changes in state convey information.
MC94MX21 Technical Data, Rev. 1.4
2
Freescale Semiconductor