MC94MX21 Datasheet, PDF (27/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Int_Clk
(reference only)
BMI_CLK/CS
BMI_D[15:0]
BMI_READ
BMI_WRITE
1+ws
1+ws
Specifications
TXD_a
TXD_b
BMI_WAIT
Figure 12. Memory Interface Master Mode, BMI Write to External Slave Device Timing with Wait Signal
(MMD_MODE_SEL=0, MASTER_MODE_SEL=1,WAIT=1)
Figure 13 shows the BMI read timing when the WAIT bit is set. As write timing, when the BMI_READ is
asserted, the BMI will detect the BMI_WAIT signal on every falling edge of the Int_Clk. When it detected
the high level of the BMI_WAIT, the BMI_READ will be negated after 1+WS Int_Clk period. If the
BMI_WAIT is always high or already high before BMI_READ is asserted, this timing will same as
without WAIT signal. So the BMI_READ will be asserted at least for 1+WS Int_Clk period.
Int_Clk
(reference only)
BMI_CLK/CS
1+ws
1+ws
BMI_D[15:0]
BMI_WRITE
RXD_a
RXD_b
BMI_READ
BMI_WAIT
Figure 13. Memory Interface Master Mode, BMI Read to External Slave Device Timing with Wait Signal
(MMD_MODE_SEL=0, MASTER_MODE_SEL=1,WAIT=1)
3.9 CSPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the CSPI1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1
or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control
Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration, SS
MC94MX21 Technical Data, Rev. 1.4
Freescale Semiconductor
27