MC94MX21 Datasheet, PDF (21/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Specifications
can write data to BMI RxFIFO anytime as CPU or DMA can move data out from RxFIFO much faster
than the BMI interface. Overflow interrupt is generated if RxFIFO overflow is detected. Once this
happens, the new coming data is ignored.
3.8.1.1.1 MMD Read BMI Timing
Figure 6 shows the MMD read BMI timing when the MMD drives clock.
On each rising edge of BMI_CLK/CS BMI checks the BMI_WRITE logic level to determine if the current
cycle is a read cycle. It puts data into the data bus and enables the data out on the rising edge of BMI_CLK/
CS if BMI_WRITE is logic high. The BMI_READ_REQ is negated one hclk cycle after the BMI_CLK/
CS rising edge of last data read. The MMD cannot issues read command when BMI_READ_REQ is low
(no data in TxFIFO).
1T
BMI_CLK/CS
BMI_READ_REQ
BMI_D[15:0]
BMI_WRITE
Tdh
Tds
TxD1 TxD2
Ts
Trh
Last TxD
Figure 6. MMD (ATI) Drives Clock, MMD Read BMI Timing
(MMD_MODE_SEL=1, MASTER_MODE_SEL=0,MMD_CLKOUT=0)
Table 13. MMD Read BMI Timing Table when MMD Drives Clock
Item
Clock period
write setup time
read_req hold time
transfer data setup time
transfer data hold time
Symbol
Minimum
Typical
Maximum
Unit
1T
33.3
–
Ts
11
–
Trh
6
–
Tds
6
–
Tdh
6
-
–
ns
–
ns
24
ns
14
ns
14
ns
Note: All the timings assume that the hclk is running at 133 MHz.
Note: The MIN period of the 1T is assumed that MMD latch data at falling edge.
Note: If the MMD latch data at next rising edge, the ideally max clock can be as much as double, but because the BMI data pads
are slow pads and it max frequency can only up to 18MHz, the max clock frequency can only up to 36 MHz.
MC94MX21 Technical Data, Rev. 1.4
Freescale Semiconductor
21