MC94MX21 Datasheet, PDF (46/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Specifications
3.15 SDRAM Memory Controller
The following figures (Figure 38 through Figure 41) and their associated tables specify the timings related
to the SDRAMC module in the i.MX21.
1
SDCLK
CS
2
3S
3
3S
RAS
CAS
WE
3H
3S
3H
3H
3S
3H
ADDR
4S 4H
ROW/BA
COL/BA
8
5
6
DQ
Data
7
3S
DQM
3H _{Note: CKE is high during the read/write cycle.}
Figure 38. SDRAM Read Cycle Timing Diagram
Table 30. SDRAM Read Cycle Timing Parameter
Ref
No.
Parameter
1 SDRAM clock high-level width
2 SDRAM clock low-level width
3 SDRAM clock cycle time
3S CS, RAS, CAS, WE, DQM setup time
3H CS, RAS, CAS, WE, DQM hold time
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
3.00
–
3
–
ns
3.00
–
3
–
ns
7.5
–
7.5
–
ns
4.78
–
3
–
ns
3.03
–
2
–
ns
MC94MX21 Technical Data, Rev. 1.4
46
Freescale Semiconductor