MC94MX21 Datasheet, PDF (20/98 Pages) Freescale Semiconductor, Inc – 333 and 350 MHz

Specifications
Ext_DMAReq
Ext_DMAGrant
t_{min_assert}
Figure 4. Assertion of DMA External Grant Signal
Figure 5 shows the safe maximum time for which External DMA request can be kept asserted, after
sensing grant signal active such that a new burst is not initiated.
Ext_DMAReq
Ext_DMAGrant
t_{max_req_assert}
Data read from
External device
t_{max_read}
Data written to
External device
t_{max_write}
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
Figure 5. Safe Maximum Timings for External Request De-Assertion
Table 12. DMA External Request and Grant Timing Parameters
Parameter
Description
3.0 V
WCS
BCS
1.8 V
Unit
WCS
BCS
t_{min_assert} Minimum assertion time of External Grant 8 hclk + 8.6 8 hclk + 2.74 8 hclk + 7.17 8 hclk + 3.25 ns
signal
t_{max_req_assert} Maximum External request assertion time 9 hclk - 20.66 9 hclk - 6.7 9 hclk - 17.96 9 hclk - 8.16 ns
after assertion of Grant signal
t_{max_read} Maximum External request assertion time 8 hclk - 6.21 8 hclk - 0.77 8 hclk - 5.84 8 hclk - 0.66 ns
after first read completion
t_{max_write} Maximum External request assertion time 3 hclk - 15.87 3 hclk - 8.83 3 hclk - 15.9 3 hclk - 9.12 ns
after completion of first write
3.8 BMI Interface Timing Diagram
3.8.1 Connecting BMI to ATI MMD Devices
3.8.1.1 ATI MMD Devices Drive the BMI_CLK/CS
In this mode MMD_MODE_SEL bit is set and MMD_CLKOUT bit is cleared. BMI_WRITE and
BMI_CLK/CS are input signals to BMI driving by ATI MMD chip set. Output signal BMI_READ_REQ
can be used as interrupt signal to inform MMD that data is ready in BMI TxFIFO for read access. MMD
MC94MX21 Technical Data, Rev. 1.4
20
Freescale Semiconductor