MC68HC05C9E Datasheet, PDF (92/106 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Specifications
SS
INPUT
SS pin of master held high.
SCK (CPOL = 0)
OUTPUT
NOTE
1
5
4
SCK (CPOL = 1)
OUTPUT
NOTE
5
4
12
12
MISO
INPUT
10 (ref)
MOSI
OUTPUT
13
MSB IN
11
MASTER MSB OUT
BITS 6–1
10
BITS 6–1
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
13
12
13
6
7
LSB IN
11 (ref)
MASTER LSB OUT
12
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SCK (CPOL = 0)
OUTPUT
SS pin of master held high.
1
5
4
SCK (CPOL = 1)
OUTPUT
5
4
MISO
INPUT
10 (ref)
MOSI
OUTPUT
13
MSB IN
11
MASTER MSB OUT
13
12
12
13
BITS 6–1
10
BITS 6–1
6
7
LSB IN
11
MASTER LSB OUT
12
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
NOTE
NOTE
Figure 12-9. SPI Master Timing Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
92
Freescale Semiconductor