MC68HC05C9E Datasheet, PDF (31/106 Pages) Freescale Semiconductor, Inc – Microcontrollers

Computer Operating Properly (COP) Reset
CM1
INTERNAL
CPU
÷4 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
CM0
CLOCK
16-BIT TIMER SYSTEM
2¹⁵
2¹³
2¹⁷
2¹⁹
COP
÷4
÷2 ÷2
÷2 ÷2
÷2 ÷2 ²²¹
COPRST
Figure 5-3. COP Block Diagram
5.4.1 COP Reset Register
The COP reset register (COPRST), shown in Figure 5-4, is a write-only register used to reset the COP.
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-4. COP Reset Register (COPRST)
The sequence required to reset the COP timer is:
• Write $55 to the COP reset register
• Write $AA to the COP reset register
Both write operations must occur in the order listed, but any number of instructions may be executed
between the two write operations provided that the COP does not time out between the two writes. The
elapsed time between software resets must not be greater than the COP timeout period. If the COP
should time out, a system reset will occur and the device will be re-initialized in the same fashion as a
power-on reset or reset.
Reading this register does not return valid data.
5.4.2 COP Control Register
The COP control register (COPCR), shown in Figure 5-5, performs these functions:
• Enables clock monitor function
• Enables COP function
• Selects timeout duration of COP timer
And flags these conditions:
• COP timeout
• Clock monitor reset
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
31