|
MC68HC05C9E Datasheet, PDF (43/106 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
|
◁ |
Timer I/O Registers
8.3.1 Timer Control Register
The timer control register (TCR), shown in Figure 8-2, performs these functions:
⢠Enables input capture interrupts
⢠Enables output compare interrupts
⢠Enables timer overflow interrupts
⢠Controls the active edge polarity of the TCAP signal
⢠Controls the active level of the TCMP output
Address: $0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
ICIE
OCIE
TOIE
IEDG
OLVL
Write:
Reset:
0
0
0
0
0
0
U
0
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
ICIE â Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on the TCAP pin. Reset clears the
ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE â Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on the TCMP pin. Reset clears the
OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE â Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG â Input Edge Bit
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin
triggers a transfer of the contents of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
OLVL â Output Level Bit
The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when
a successful output compare occurs. Reset clears the OLVL bit.
1 = TCMP goes high on output compare.
0 = TCMP goes low on output compare.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
43
|
▷ |