MC68HC05C9E Datasheet, PDF (54/106 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface (SCI)
9.9 Start Bit Detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as the start
edge verification samples in Figure 9-4). If at least two of these three verification samples detect a logic 0,
a valid start bit has been detected; otherwise, the line is assumed to be idle. A noise flag is set if all three
verification samples do not detect a logic 0. Thus, a valid start bit could be assumed with a set noise flag
present.
If a framing error has occurred without detection of a break (10 0s for 8-bit format or 11 0s for 9-bit format),
the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register is inverted to a logic 1, and the three logic 1 start
qualifiers (shown in Figure 9-4) are forced into the sample shift register during the interval when detection
of a start bit is anticipated (see Figure 9-6); therefore, the start bit will be accepted no sooner than it is
anticipated.
DATA
RDI
EXPECTED STOP
ARTIFICIAL EDGE
DATA
START BIT
DATA SAMPLES
a) Case 1: Receive Line Low During Artificial Edge
DATA
RDI
EXPECTED STOP
START EDGE
DATA
START BIT
DATA SAMPLES
b) Case 2: Receive Line High During Expected Start Edge
Figure 9-6. SCI Artificial Start Following a Frame Error
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $003B) produced the
framing error, the start bit will not be artificially induced and the receiver must actually detect a logic 1
before the start bit can be recognized (see Figure 9-7).
EXPECTED STOP
BREAK
RDI
DETECTED AS VALID START EDGE
START BIT
DATA SAMPLES
START START EDGE
QUALIFIERS VERIFICATION
SAMPLES
Figure 9-7. SCI Start Bit Following a Break
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
54
Freescale Semiconductor