MC68HC05C9E Datasheet, PDF (89/106 Pages) Freescale Semiconductor, Inc – Microcontrollers

IRQ PIN
t_ILIL
t_ILIH
Control Timing
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t_ILIH) is either 125 ns (f_OP = 2.1 MHz)
or 250 ns (f_OP = 1 MHz). The period t_ILIL should not be less than the number of t_CYC cycles it takes to
execute the interrupt service routine plus 19 t_CYC cycles.
IR.Q1
t_ILIH
NORMALLY
USED WITH
.
.
WIRED-OR
IRQN
CONNECTION
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low,
the next interrupt is recognized.
Figure 12-5. External Interrupt Timing
OSC⁽¹⁾
t_RL
RESET
t_ILIH
IRQ⁽²⁾
IRQ⁽³⁾
4064 t_CYC
INTERNAL
CLOCK
$3FFE
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF4
Notes:
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
RESET OR INTERRUPT
VECTOR FETCH
Figure 12-6. Stop Recovery Timing Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
89