MC68HC05C9E Datasheet, PDF (26/106 Pages) Freescale Semiconductor, Inc – Microcontrollers

Interrupts
Table 4-1. Vector Addresses for Interrupts and Resets
Function
Reset
Software interrupt (SWI)
External interrupt
Timer interrupts
SCI interrupts
SPI interrupts
Source
Power-on reset
RESET pin
COP watchdog
User code
IRQ pin
Port B pins
ICF bit
OCF bit
TOF bit
TDRE bit
TC bit
RDRF bit
OR bit
IDLE bit
SPIF bit
MODF bit
Local Mask
None
None
None
ICIE bit
OCIE bit
TOIE bit
TCIE bit
RIE bit
ILIE bit
SPIE bit
Global Mask
None
None
I bit
I bit
I bit
I bit
Priority
(1 = Highest)
1
Same priority
as instruction
2
3
4
5
Vector
Address
$3FFE–$3FFF
$3FFC–$3FFD
$3FFA–$3FFB
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
4.3 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled.
Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge
of IRQ. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB.
When any of the port B pullups are enabled, each pin becomes an additional external interrupt source
which is executed identically to the IRQ pin. Port B interrupts follow the same edge/edge-level selection
as the IRQ pin. The branch instructions BIL and BIH also respond to the port B interrupts in the same way
as the IRQ pin. See 7.3 Port B.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger operation is
selectable. The sensitivity is software-controlled by the IRQ bit in the option register ($3FDF).
NOTE
The internal interrupt latch is cleared in the first part of the interrupt service
routine; therefore, one external interrupt pulse can be latched and serviced
as soon as the I bit is cleared.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
26
Freescale Semiconductor