33874 Datasheet, PDF (9/37 Pages) Freescale Semiconductor, Inc – Quad High-Side Switch (Quad 35 mΩ)

ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ V_PWR ≤ 27 V, 4.5 V ≤ V_DD ≤ 5.5 V, -40°C ≤ T_A ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI)
Input Logic High Voltage ⁽¹³⁾
Input Logic Low Voltage ⁽¹³⁾
Input Logic Voltage Hysteresis ⁽¹⁴⁾
V_IH
0.7 V_DD
–
–
V
V_IL
–
–
0.2 V_DD
V
V_IN(HYS)
100
850
1200
mV
Input Logic Pulldown Current (SCLK, SI, IN[0:3], V_IN>0.2 V_DD)
I_DWN
5.0
–
20
µA
RST Input Voltage Range
SO, FS Tri-State Capacitance ⁽¹⁴⁾
V_RST
C_SO
4.5
5.0
5.5
V
–
–
20
pF
Input Logic Pulldown Resistor (RST) and WAKE
Input Capacitance ⁽¹⁵⁾
Wake Input Clamp Voltage ⁽¹⁶⁾
R_DWN
100
200
400
kΩ
C_IN
–
4.0
12
pF
V_CL(WAKE)
V
I_CL(WAKE) < 2.5 mA
7.0
–
14
Wake Input Forward Voltage
V_F(WAKE)
V
I_CL(WAKE) = -2.5 mA
- 2.0
–
- 0.3
SO High-State Output Voltage
V_SOH
V
I_OH = 1.0 mA
0.8 V_DD
–
–
FS, SO Low-State Output Voltage
V_SOL
V
I_OL = -1.6 mA
–
0.2
0.4
SO Tri-State Leakage Current
I_SO(LEAK)
µA
CS > 0.7 V_DD, 0<V_SO<V_DD
Input Logic Pullup Current ⁽¹⁷⁾
- 5.0
0
5.0
I_UP
µA
CS, V_IN < 0.7 V_DD
FSI Input pin External Pulldown Resistance ⁽¹⁸⁾
5.0
–
20
R_FS
kΩ
FSI Disabled, HS[0:3] state according to direct inputs state and SPI
INx_SPI bits and A/O_s bit
FSI Enabled, HS[0:3] OFF
FSI Enabled, HS0 ON, HS[1:3] OFF
FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
–
0
1.0
6.0
6.5
7.0
15
17
19
40
Infinite
–
Temperature Feedback
T_A = 25°C
Temperature Feedback Derating
T_FEED
V
3.8
3.9
4.0
DT_FEED
-7.2
-7.5
-7.8
mV/°C
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST
signals may be supplied by a derived voltage referenced to V_PWR.
14. No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested.
15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
16. The current must be limited by a series resistance when using voltages > 7.0 V.
17. Pullup current is with CS OPEN. CS has an active internal pullup to VDD.
18. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the
resistance value will always be within the desired (specified) range.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33874
9