33874 Datasheet, PDF (17/37 Pages) Freescale Semiconductor, Inc – Quad High-Side Switch (Quad 35 mΩ)

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),
and Chip Select (CS).
The SI / SO pins of the 33874 follow a first-in first-out (D15
to D0) protocol, with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
CCSSB
CS
SCLK
SI
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
NOTES: 1. ^2.R^DST¹B⁵i^:s^Din⁰a^rlo^eg^laic^teH s^totat^te^hd^eur^ming^osth^te^ra^eb^co^eve^ntop^oe^rr^da^etio^rn^e.^{d entry of data into the device.}
2. 3.DO,DD115, D:2O, D...0, arnedlaDt1e5troelathteetofitrhsetm1o6stbreitcsenotfoordredredreedntrfyaouflpt raognrdamstdaatuasintdoathtae LdoUeuXvtiIcoCef.the device.
Figure 9. Single 16-Bit Word SPI Communication
OPERATIONAL MODES
The 33874 has four operating modes: Sleep, Normal,
Fault, and Fail-Safe. Table 5 summarizes details contained in
succeeding paragraphs.
Table 5. Fail-Safe Operation and Transitions to Other
33874 Modes
Mode FS Wake RST WDTO
Comments
Sleep x 0
Normal 1 x
Fault 0 1
01
00
10
11
11
Fail-
Safe
x = Don’t care.
0
x Device is in Sleep mode. All
outputs are OFF
1 No Normal mode. Watchdog is
active if enabled.
1 No Device is currently in fault
0
mode. The faulted output(s)
is (are) OFF.
1
1
Watchdog has timed out and
1
the device is in Fail-Safe
Mode. The outputs are as
0
configured with the RFS
Yes _{resistor connected to FSI.}
RST and WAKE must go
from logic [1] to logic [0]
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied the
FSI pin to ground.
SLEEP MODE
The Default mode of the 33874 is the Sleep mode. This is
the state of the device after first applying battery voltage
(V_PWR) prior to any I/O transitions. This is also the state of the
device when the WAKE and RST are both logic [0]. In the
Sleep mode, the output and all unused internal circuitry, such
as the internal 5.0 V regulator, are off to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to logic [0]. The 33874 will transition to the
Normal or Fail-Safe operating modes based on the WAKE
and RST inputs as defined in Table 5.
NORMAL MODE
The 33874 is in Normal mode when:
• V_PWR and V_DD are within the normal voltage range.
• RST pin is logic [1].
• No fault has occurred.
FAIL-SAFE MODE
FAIL-SAFE MODE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input pin
transitions from logic [0] to logic [1]. The WAKE input is
capable of being pulled up to V_PWR with a series of limiting
Analog Integrated Circuit Device Data
Freescale Semiconductor
33874
17