33874 Datasheet, PDF (11/37 Pages) Freescale Semiconductor, Inc – Quad High-Side Switch (Quad 35 mΩ)

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ V_PWR ≤ 27 V, 4.5 V ≤ V_DD ≤ 5.5 V, - 40°C ≤ T_A ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued)
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time ⁽²⁴⁾
Watchdog Timeout ⁽²⁵⁾
WD[1:0] : 00
WD[1:0] : 01
WD[1:0] : 10
WD[1:0] : 11
Direct Input Switching Frequency (DICR D3 = 0)
SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO)
t_OCH
1.0
5.0
20
µs
t _CNSVAL
–
–
10
µs
ms
t _WDTO0
t _WDTO1
t _WDTO2
t _WDTO3
446
223
1800
900
558
279
2250
1125
725
363
2925
1463
f_PWM
-
300
-
Hz
Maximum Frequency of SPI Operation
f _SPI
–
Required Low State Duration for RST ⁽²⁶⁾
t _WRST
–
Rising Edge of CS to Falling Edge of CS (Required Setup Time) ⁽²⁷⁾
t _CS
–
Rising Edge of RST to Falling Edge of CS (Required Setup Time) ⁽²⁷⁾
t _ENBL
–
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) ⁽²⁷⁾
t _LEAD
–
Required High State Duration of SCLK (Required Setup Time) ⁽²⁷⁾
t _WSCLKh
–
Required Low State Duration of SCLK (Required Setup Time) ⁽²⁷⁾
t _WSCLKl
–
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) ⁽²⁷⁾
t _LAG
–
SI to Falling Edge of SCLK (Required Setup Time) ⁽²⁸⁾
t _{SI (SU)}
–
Falling Edge of SCLK to SI (Required Setup Time) ⁽²⁸⁾
t _{SI (HOLD)}
–
SO Rise Time
t _RSO
C_L = 200 pF
–
SO Fall Time
t _FSO
C_L = 200 pF
–
SI, CS, SCLK, Incoming Signal Rise Time ⁽²⁸⁾
t _RSI
–
SI, CS, SCLK, Incoming Signal Fall Time ⁽²⁸⁾
t _FSI
–
Time from Falling Edge of CS to SO Low Impedance ⁽²⁹⁾
t _SO(EN)
–
Time from Rising Edge of CS to SO High Impedance ⁽³⁰⁾
t _SO(DIS)
–
Time from Rising Edge of SCLK to SO Data Valid ⁽³¹⁾
t _VALID
0.2 V_DD ≤ SO ≤ 0.8 V_DD, C_L = 200 pF
–
–
3.0
MHz
50
350
ns
–
300
ns
–
5.0
µs
50
167
ns
–
167
ns
–
167
ns
50
167
ns
25
83
ns
25
83
ns
ns
25
50
ns
25
50
–
50
ns
–
50
ns
–
145
ns
65
145
ns
ns
65
105
Notes
24. Time necessary for the CSNS to be with ±5% of the targeted value.
25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t _WDTO is consistent for all configured
watchdog timeouts.
26. RST low duration measured with outputs enabled and going to OFF or disabled condition.
27. Maximum setup time required for the 33874 is the minimum guaranteed time needed from the microcontroller.
28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
29. Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.
30. Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.
31. Time required to obtain valid data out from SO following the rise of SCLK.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33874
11