33874 Datasheet, PDF (22/37 Pages) Freescale Semiconductor, Inc – Quad High-Side Switch (Quad 35 mΩ)

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to
the section entitled Serial Output Communication (Device
Status Return Data) beginning on page 23.)
ADDRESS 00001— OUTPUT CONTROL REGISTER
(OCR0)
The OCR0 register allows the MCU to control the ON / OFF
state of four outputs through the SPI. Incoming message bit
D3 : D0 reflects the desired states of the four high-side
outputs (INx_SPI), respectively. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF.
ADDRESS 01001— OUTPUT CONTROL REGISTER
(OCR1)
Incoming message bits D3 : D0 reflect the desired output
that will be mirrored on the Current Sense (CSNS) pin. A
logic [1] on message bits D3 : D0 enables the CSNS pin for
outputs HS3 : HS0, respectively. In the event the current
sense is enabled for multiple outputs, the current will be
summed. In the event that bits D3 : D0 are all logic [0], the
output CSNS will be tri-stated. This is useful when several
CSNS pins of several devices share the same A /D converter.
ADDRESS A₁A₀010 — SELECT OVERCURRENT
HIGH AND LOW REGISTER (SOCHLR_S)
The SOCHLR_s register allows the MCU to configure the
output overcurrent low and high detection levels,
respectively. Each output “s” is independently selected for
configuration based on the state of the D12 : D11 bits
(Table 10).
Table 10. Output Selection
A₁ (D12)
A₀ (D11)
0
0
0
1
1
0
1
1
HS_s
HS0
HS1
HS2
HS3
Each output can be configured to different levels. In
addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements matching system characteristics. Bits D2 : D0
set the overcurrent low detection level to one of eight possible
levels, as shown in Table 11, page 22. Bit D3 sets the
overcurrent high detection level to one of two levels, as
outlined in Table 12, page 22.
Table 11. Overcurrent Low Detection Levels
SOCL2_s* SOCL1_s* SOCL0_s*
(D2)
(D1)
(D0)
Overcurrent Low
Detection (Amperes)
HS0 to HS3
0
0
0
10
0
0
1
8.9
0
1
0
7.9
0
1
1
7.0
1
0
0
5.8
1
0
1
4.8
1
1
0
3.9
1
1
1
2.8
* “_s” refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 22.
Table 12. Overcurrent High Detection Levels
SOCH_s* (D3)
Overcurrent High Detection (Amperes)
HS0 to HS3
0
55
1
40
* “_s” refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 22.
ADDRESS A₁A₀011 — CURRENT DETECTION TIME
AND OPEN LOAD REGISTER (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an overcurrent low
condition before an output latches OFF. Each output is
independently selected for configuration based on A₁A₀ ,
which are the state of the D12 : D11 bits (refer to Table 10,
page 22).
Bits D1:D0 (OCLT1_s:OCLT0_s) allow the MCU to select
one of three overcurrent fault blanking times defined in
Table 13. Note that these timeouts apply only to the
overcurrent low detection levels. If the selected overcurrent
high level is reached, the device will latch off within 20 µs.
Table 13. Overcurrent Low Detection Blanking Time
OCLT[1:0]_s*
Timing
00
155 ms
01
Do not use
10
75 ms
11
150 µs
* “_s” refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 22.
33874
22
Analog Integrated Circuit Device Data
Freescale Semiconductor